Lead/Staff Engineer – Synthesizable IP for Emulation & FPGA Prototyping

About this job

Qualcomm is hiring a Lead or Staff Engineer in Bengaluru to lead synthesizable IP models for hardware emulation and FPGA prototyping platforms. These let software teams start work before chips exist.

You will shape architecture, write and tune Verilog/SystemVerilog RTL, keep C/C++ reference models aligned with RTL and drive bring-up across simulation, emulation and FPGA. You will also own planning and risk for your projects. The role is in the office.

Eligibility

• 5+ years in ASIC, SoC or FPGA design, RTL or prototyping
• Strong Verilog/SystemVerilog synthesizable design
• C/C++ reference models and validation
• Xilinx FPGA flows with Vivado and emulators like Veloce or ZeBu
• Bus protocols such as AXI, AHB and APB; Git and scripting

Skills required

What you will do

• Lead design of IP models for emulation and FPGA
• Write and optimise RTL for timing and area
• Keep C/C++ models aligned with RTL
• Drive integration, debug and bring-up
• Plan projects and manage technical risk

How to apply

• Open the official Qualcomm job page with the Apply button and submit your application there.
• Tailor your resume to IP or SoC blocks you designed, FPGA or emulation bring-ups you led and results.

Before the interview, prepare:

• Writing synthesizable RTL: what to avoid
• FPGA timing closure in Vivado
• Transaction-based emulation: SCE-MI and DPI-C
• Partitioning a design across several FPGAs

Apply on official website →

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Posted 12 Nov 2026 · Last checked 13 Nov 2026 · Official source