Senior Engineer – Static Timing Analysis (STA) Signoff
Qualcomm · Chennai
| Company | Qualcomm |
|---|---|
| Role | Senior Engineer – Static Timing Analysis (STA) Signoff |
| Location | Chennai |
| Work mode | On-site |
| Experience | 1–3 years |
| Job type | Full-time |
About this job
Qualcomm is hiring a Senior Engineer for static timing analysis (STA) in Chennai, in its hardware engineering group. You will set up, run and sign off timing for multi-mode, multi-voltage SoC and subsystem designs.
The work covers timing debug across process, voltage and temperature corners with PrimeTime and Tempus, Spice correlation, timing ECOs and flow automation in TCL, Perl or Python. You will work with design, DFT, synthesis and physical design teams. The role is in the office.
Eligibility
- Bachelor's with 2+ years, or master's with 1+ year, of hardware engineering
- B.Tech, M.Tech or MS in electronics, microelectronics or VLSI
- STA setup and signoff with PrimeTime or Tempus
- Clock gating, power gating and multi-voltage design
- Scripting in TCL, Perl or Python
Skills required
What you will do
- Set up STA and drive timing signoff
- Debug timing across PVT corners
- Correlate Spice and STA results
- Handle timing ECOs and equivalence checks
- Automate STA and physical design flows
How to apply
- Open the official Qualcomm job page with the Apply button and submit your application there.
- Tailor your resume to SoC blocks you signed off for timing, the tools you used and ECOs you closed.
Before the interview, prepare:
- Setup vs hold violations and how to fix each
- OCV, AOCV and POCV in signoff
- Multi-mode multi-corner analysis
- Clock domain crossing and false paths
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