Staff Engineer – Design Verification for SoC Infrastructure IP (DDR, Memory Controllers)
Qualcomm · Bengaluru
| Company | Qualcomm |
|---|---|
| Role | Staff Engineer – Design Verification for SoC Infrastructure IP (DDR, Memory Controllers) |
| Location | Bengaluru |
| Work mode | On-site |
| Experience | 3–6 years |
| Job type | Full-time |
About this job
Qualcomm is hiring a Staff Engineer for design verification in Bengaluru. You will verify next-generation infrastructure IP such as DDR subsystems and memory controllers that go into chips for phones, tablets and other devices.
You will own UVM test benches with checkers, scoreboards and assertions, write test plans, close code and functional coverage, debug regressions with design teams, use tools like Certitude and VC Formal, and help debug issues after silicon. The role is in the office.
Eligibility
- Bachelor's with 4+ years, master's with 3+, or PhD with 2+ in hardware engineering
- Expert UVM-based verification in SystemVerilog
- ARM bus protocols, virtual memory and SoC architecture
- Building monitors, scoreboards and sequencers
- Plus: low-power design, ASIL, Python/Perl and post-silicon debug
Skills required
What you will do
- Own the IP verification test bench
- Write test plans and close coverage
- Debug regressions with design teams
- Build verification scripts and tools
- Support post-silicon debug and sign-off
How to apply
- Open the official Qualcomm job page with the Apply button and submit your application there.
- Tailor your resume to IPs you verified, coverage you closed and bugs your test benches caught.
Before the interview, prepare:
- UVM phases and sequences
- Functional vs code coverage closure
- Verifying a DDR memory controller
- Writing SystemVerilog assertions
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