Analog Design Flow & Infrastructure Automation Manager
Intel · Bengaluru
| Company | Intel |
|---|---|
| Role | Analog Design Flow & Infrastructure Automation Manager |
| Location | Bengaluru |
| Work mode | Hybrid |
| Experience | 6+ years |
| Job type | Full-time |
| Qualification | Bachelor's or Master's in Electrical Engineering, Computer Engineering or related field |
About this job
Intel is hiring an Analog Design Automation Manager in Bengaluru to lead the design environments and CAD infrastructure used for analog and mixed-signal chips. The role owns EDA tools, PDK integration, compute farms and the data that goes into every tapeout.
You will keep design flows reproducible and audit-ready, manage Linux compute and licence servers, control tool and PDK versions, and lead a team of design automation and infrastructure engineers. The role is hybrid.
Eligibility
- 10+ years in analog or mixed-signal design or CAD support
- 5+ years of leadership experience
- Hands-on Virtuoso, p-cell development, layout, LVS, DRC and PDK work
- Strong Linux administration and scripting in Python, Tcl, Shell or SKILL
- Experience with compute grids, storage, licence servers and version control
Skills required
What you will do
- Own analog design flows for schematic, layout, verification and extraction
- Run Linux compute farms, LSF scheduling, storage and FlexLM licences
- Govern design data, backups and tapeout manifests
- Qualify tool and PDK upgrades before production rollout
- Lead and mentor engineers and manage EDA vendors
How to apply
- Open the official Intel job page with the Apply button and submit your application there.
- Tailor your resume to EDA environments and CAD infrastructure you ran, the flows you automated and the teams you led.
Before the interview, prepare:
- Analog flow: schematic, layout, DRC, LVS and parasitic extraction
- Tapeout readiness: freezing tool, PDK and deck versions
- Grid computing: LSF queues, job priorities and licence usage
- Reproducibility: capturing environments and versioning PDK overlays
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