ASIC Design Verification Engineer – Silicon One (UVM, Simulation)
Cisco · Bengaluru
| Company | Cisco |
|---|---|
| Role | ASIC Design Verification Engineer – Silicon One (UVM, Simulation) |
| Location | Bengaluru |
| Work mode | On-site |
| Experience | 6+ years |
| Job type | Full-time |
About this job
Cisco is hiring an ASIC Design Verification Engineer in Bengaluru for the Silicon One group, which builds the chips, optics and hardware behind Cisco's switching, routing and wireless products.
You will plan and run verification using simulation, with emulation used to speed up large tests. You will build test benches, work with designers to fix bugs, improve verification automation and mentor others. The role is in the office.
Eligibility
- Bachelor's with 7+ years, master's with 4+, or PhD with 1+ year of related work
- Strong verification with UVM or OVM
- Simulation-based test bench development
- Emulation platform experience
- Close work with design and validation teams
Skills required
What you will do
- Build verification plans and test benches for simulation
- Run large tests, including on emulation
- Debug design bugs with design engineers
- Improve verification tools and automation
- Document results and coach junior engineers
How to apply
- Open the official Cisco job page with the Apply button and submit your application there.
- Tailor your resume to networking or large ASICs you verified and how you closed coverage.
Before the interview, prepare:
- UVM register model and reusable verification components
- Constrained random testing and seeds
- Coverage-driven verification in practice
- Networking chip blocks: parsers, queues and packet buffers
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